The present invention relates to treating a low dielectric constant layer suitable for use in semiconductor devices. The present invention has particular applicability to the formation of interlevel dielectric layers in multilevel semiconductor devices.
The escalating requirements for high density and performance associated with ultra-large scale integration semiconductor devices necessitate design features of 0.18 micron and under, increased transistor and circuit speeds, high reliability, and increased manufacturing throughput. The reduction of design features to 0.18 micron and under challenges the limitations of conventional interconnection technology, such as the electrical isolation properties of interlevel dielectric (ILD) materials.
A problem encountered in highly miniaturized semiconductor devices employing multiple levels and reduced interwiring spacings in both the horizontal and vertical dimensions is related to the resistance-capacitance (RC) time constant of the system. Although semiconductor devices are presently being scaled in the horizontal dimension, they are not generally scaled in the vertical dimension, since scaling in both dimensions would lead to a higher current density that could exceed reliability limits. Horizontal scaling, however, requires conductive lines having a high aspect ratio, i.e., ratios of conductor height to conductor width greater than one, e.g., three or four, along with reduced interwiring spacings. As a consequence, capacitive coupling between conductive lines becomes a significant limitation on circuit speed. If intrametal capacitance is high, electrical inefficiencies and inaccuracies increase. It has been recognized that a reduction in capacitance within multi-level system will reduce the RC time constant between the conductive lines.
The drive towards increased miniaturization and the resultant increase in the RC time constant have served as an impetus for the development of newer, low dielectric constant (xe2x80x9clow kxe2x80x9d) materials as substitutes for conventional higher dielectric constant silicon oxide-based ILD materials. However, such dielectric materials must be able to serve a number of different purposes requiring diverse characteristics and attributes. For example, the ILD material must form adherent films that: prevent unwanted shorting of neighboring conductors or conducting levels by acting as a rigid, insulating spacer; prevent corrosion and/or oxidation of metal conductors, by acting as a barrier to moisture and mobile ions; fill deep, narrow gaps between closely spaced conductors; and undergo planarization of uneven surface topography so that a relatively flat level of conductors can be reliably deposited thereon. Another, and important consideration in regard to RC time constant effects, is that such dielectric films used as ILD materials must have a low dielectric constant, as compared to the value of 4.1 to 3.9 for a conventionally employed silicon dioxide (SiO2) layer, in order to reduce the RC time constant, lower power consumption, reduce crosstalk, and reduce signal delay in closely spaced conductors.
Silicon oxide has found the widest application as ILD layers in multilevel interconnect technology partly because of the familiarity and varied methods for depositing silicon oxide layers pervasive in semiconductor manufacturing processes. Silicon oxide as ILD layers can be deposited by any number of processes, including chemical vapor deposition (CVD), plasma enhanced CVD and liquid spin-on glass forming techniques, tailored to achieving high-quality ILDs characterized by good electrical and physical properties.
Increasing attention has focused on the use of low k dielectrics, such as porous silicon dioxides in combination with copper metallization to reduce feature size, increase circuit density and improve device performance. However, the use of such copper/silicon oxide composite structures is not without problems. Copper is known to have a relatively large diffusion coefficient into silicon oxide and silicon and the propensity of copper ions to diffuse or migrate into such materials adversely affects their dielectric strength. For this reason, copper and copper alloys are typically encapsulated by at least one diffusion barrier to prevent diffusion of the copper and/or copper ions into silicon oxide layers. Use of barrier layers, however, further reduces the shrinking space available for patterned metallization and conductive features and increases the need for improved dielectric materials separating the conductive features.
Additional difficulties in the employment of low k materials lie in the surface properties of the low k dielectric layer. For example, it has been observed that, under certain circumstances, adding a protective capping layer on a low k dielectric layer results in poor adhesion. It has been also observed that applying the capping layer by conventional plasma deposition techniques can cause an underlying low k layer, particularly a porous dielectric underlayer, to degrade due to the oxidation attendant during the formation of the capping layer. The degradation is due to bond breaking and loss of hydrogen and/or methyl groups in contained in such materials when oxygen or oxygen radicals react with the surface of an underlying low k layer.
Thus, there exists a need for utilizing current techniques of forming ILD layers having low dielectric constants that have improved surface properties for improved adhesion and improved resistance to metal contamination, particularly as employed in the manufacture of ultra large scale integration semiconductor devices having multiple levels.
An advantage of the present invention is a semiconductor device having a low k material with improved surface properties including resistance to degradation, improved adhesion to subsequently applied layers thereon and improved resistance to metal contamination.
Additional advantages, and other features of the present invention will be set forth in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method of forming a composite dielectric on a semiconductor substrate. The composite dielectric comprises a first dielectric, e.g. a low k dielectric such as a porous silicon oxide, and a cap layer, e.g. a silicon nitride or silicon oxynitride, over the low k dielectric. The method comprises: forming a dielectric layer having an exposed surface on the substrate; subjecting the dielectric layer to phosphine gas and/or a phosphine plasma to treat the exposed surface thereof; and forming a cap layer directly on the treated surface of the dielectric layer.
The present method provides for introducing the substrate to a plasma enhanced chemical vapor deposition (PECVD) chamber having a phosphine source to subject the exposed surface of the dielectric layer to the phosphine and/or phosphine plasma and forming the cap layer by PECVD. Advantageously, the present invention contemplates that the phosphine plasma treatment and cap formation can be carried out in the same PECVD chamber by sequential steps thereby minimizing process steps, contamination and process variation.
The side surfaces, after etching the dielectric layer, can also enjoy the benefit of the present invention. In an embodiment of the present invention, a photoresist is deposited and patterned on a cap layer followed by etching through the cap and dielectric layers to expose side surfaces on the cap and dielectric layers. The exposed side surfaces of the dielectric layer are then subject to a phosphine plasma to improve the surface properties thereof.
Another aspect of the present invention is a method of treating a dielectric layer on a semiconductor substrate. The present invention contemplates forming a dielectric layer on a semiconductor substrate, such as a substrate that includes a single crystal silicon substrate having at least one active device region formed therein or thereon. The method comprises: forming a dielectric layer on the substrate; forming a patterned photoresist on the dielectric layer; etching through the dielectric layer to expose side surfaces therein; and subjecting the side surfaces of the dielectric layer to a phosphine plasma.
Embodiments include removing the photoresist layer; forming a conformal barrier layer on the dielectric layer including the phosphine plasma treated side surfaces thereof; forming a conductive layer on the conformal barrier layer and within the etched dielectric layer; annealing the conductive layer; polishing the conductive layer and continuing through to the barrier layer to form a conductive trench or plug within the dielectric layer; and forming a cap layer over the conductive layer and barrier layer.
Additional advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiments of the present invention are shown and described, simply by way of illustration but not limitation. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modification in various obvious respects, all without departing from the spirit of the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.